`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/06/23 17:30:05
// Design Name: 3-to-8 Decoder
// Module Name: decoder_3to8
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// 3-to-8 Decoder with 3-bit input and 8-bit output
// 
//////////////////////////////////////////////////////////////////////////////////
//3-8译码器
module decoder_3to8 (
    input [2:0] A,        // 3-bit input
    output reg [7:0] Y    // 8-bit output
);

    always @(*) 
    begin
        case(A)
            3'b000: Y = 8'b00000001;  // A = 000 -> Y = 00000001
            3'b001: Y = 8'b00000010;  // A = 001 -> Y = 00000010
            3'b010: Y = 8'b00000100;  // A = 010 -> Y = 00000100
            3'b011: Y = 8'b00001000;  // A = 011 -> Y = 00001000
            3'b100: Y = 8'b00010000;  // A = 100 -> Y = 00010000
            3'b101: Y = 8'b00100000;  // A = 101 -> Y = 00100000
            3'b110: Y = 8'b01000000;  // A = 110 -> Y = 01000000
            3'b111: Y = 8'b10000000;  // A = 111 -> Y = 10000000
            default: Y = 8'b00000000; // 默认情况下，输出为 00000000
        endcase
    end

endmodule

